Complex circuitry such as high speed computer systems, automatic test equipment, VLSI chips, synchronous machines, self timed RAMS, wafer scale integration circuits and module or board level designs all require clock signals to synchronize the components of the complex circuitry. Because of the difference of the times of propagation of the various elements of a clock distribution circuit for high-to-low and low-to-high transitions, the pulse widths of a clock signal are distorted (skew) by each element through which the clock signal passes. Clock skew is one of the major concerns in high speed digital system design. If two circuits are clocked by two outputs of the same clock drive with relatively large skew, they receive the clock signal at different times. Clock skew system timing problems can then be encountered unless the clock period is much larger than the skew. Consequently, clock skew sets an upper limit on the frequency and the operating speed of the system. At high frequencies the ability of the designer fanout and low skew can be used to improve matching and reduce the physical size of the system.
Thus, what is needed is a circuit for distributing a clock signal to a plurality of other circuits, wherein the skew between the input signal and the plurality of output signals is substantially reduced.